Recovery in Multicomputers with Finite Error Detection Latency
نویسندگان
چکیده
P. Krishna N. H. Vaidya D. K. Pradhan Computer Science Department Texas A&M University College Station, TX 77843-3112 Abstract In most research on checkpointing and recovery, it has been assumed that the processor halts immediately in response to any internal failure (fail-stop model). This paper presents a recovery scheme (independent checkpointing and message logging) for a multicomputer system consisting of processors having a nonzero error detection latency. Our scheme tolerates bounded error detection latencies, thus, achieving a higher fault coverage. The simulation results show that for typical detection latency values, the recovery overhead is almost independent of the detection latency.
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